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freescale semiconductor data sheet: advance information document number: MR0A16A rev. 0, 6/2007 freescale semiconductor, inc., 2007. all rights reserved. this document contains information on a new product under development. freescale reserves the right to change or discontinue this product without notice. introduction the MR0A16A is a 1,048,576-bit magnetoresistive random access memory (mram) device organized as 65,536 words of 16 bits. the MR0A16A is equipped with chip enable ( e), write enable ( w), and output enable ( g) pins, allowing for significant system design flexibility without bus contention. because the MR0A16A has separate byte-enable controls ( lb and ub), individual bytes can be written and read. mram is a nonvolatile memory technology that protects data in the event of power loss and does not require periodic refreshing. the MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical data quickly. the MR0A16A is available in a 400-mil, 44-lead plastic small-outline tsop type-ii package with an industry-standard center power and ground sram pinout. the MR0A16A is available in commercial (0?c to 70?c), industrial ( - 40?c to 85?c) and extended ( - 40?c to 105?c) ambient temperature ranges. features single 3.3-v power supply commercial temperature range (0?c to 70?c), industrial temperature range ( - 40?c to 85?c) and extended temperature range ( - 40?c to 105?c) symmetrical high-speed read and write with fast access time (35 ns) flexible data bus control ?8 bit or 16 bit access equal address and chip-enable access times automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss all inputs and outputs are transistor-transistor logic (ttl) compatible fully static operation full nonvolatile operation with 20 years minimum data retention 64k x 16-bit 3.3-v asynchronous magnetoresistive ram MR0A16A 44-tsop case 924a-02
MR0A16A advanced information data sheet, rev. 0 2 freescale semiconductor device pin assignment figure 1. block diagram device pin assignment figure 2. MR0A16A in 44-pin tsop type ii package upper byte output enable lower byte output enable column decoder row decoder 64k x 16 bit memory array final write drivers sense amps upper byte write enable lower byte write enable output enable buffer chip enable buffer write enable buffer byte enable buffer address buffers upper byte output buffer lower byte output buffer upper byte write driver lower byte write driver dql[7:0] dqu[15:8] g e w ub lb 8 8 8 8 8 8 16 16 16 a[15:0] 8 8 8 8 ub lb 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a15 a14 a13 g ub lb dqu15 dqu14 dqu13 dqu12 v ss v dd dqu11 dqu10 dqu9 dqu8 nc v dd v ss a12 a11 a10 a0 a1 a2 a3 a4 e dql0 dql1 dql2 dql3 v dd v ss dql4 dql5 dql6 dql7 w a5 a6 a7 a8 a9 table 1. pin functions signal name function a[15:0] address input e chip enable w write enable g output enable ub upper byte select lb lower byte select dql[7:0] data i/o, lower byte dqu[15:8] data i/o, upper byte v dd power supply v ss ground nc do not connect this pin
electrical specifications MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 3 electrical specifications absolute maximum ratings this device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (hi-z) circuits. the device also contains protection against external magnetic fields. precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. table 2. operating modes e 1 g 1 w 1 lb 1 ub 1 mode v dd current dql[7:0] 2 dqu[15:8] 2 hxxxx not selected i sb1 , i sb2 hi-z hi-z l h h x x output disabled i dda hi-z hi-z l x x h h output disabled i dda hi-z hi-z llhlhlower b yte read i dda d out hi-z l l h h l upper byte read i dda hi-z d out l l h l l word read i dda d out d out l x l l h lower byte write i dda d in hi-z l x l h l upper byte write i dda hi-z d in l x l l l word write i dda d in d in notes: 1 h = high, l = low, x = don? care 2 hi-z = high impedance
MR0A16A advanced information data sheet, rev. 0 4 freescale semiconductor electrical specifications table 3. absolute maximum ratings 1 parameter symbol value unit supply voltage 2 v dd ?.5 to 4.0 v voltage on any pin 2 v in ?.5 to v dd + 0.5 v output current per pin i out 20 ma package power dissipation 3 p d 0.600 w temperature under bias MR0A16Ays35 (commercial) MR0A16Acys35 (industrial) MR0A16Avys35 (extended) t bias ?0 to 85 ?5 to 95 ?5 to 110 ?c storage temperature t stg ?5 to 150 ?c lead temperature during solder (3 minute max) t lead 260 ?c maximum magnetic ?ld during write MR0A16Ays35 (commercial) MR0A16Acys35 (industrial) MR0A16Avys35 (extended) h max_write 15 25 25 oe maximum magnetic ?ld during read or standby MR0A16Ays35 (commercial) MR0A16Acys35 (industrial) MR0A16Avys35 (extended) h max_read 100 100 100 oe notes: 1 permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating conditions. exposure to excessive voltages or magnetic fields could affect device reliability. 2 all voltages are referenced to v ss . 3 power dissipation capability depends on package characteristics and use environment. table 4. operating conditions parameter symbol min typ max unit power supply voltage v dd 3.0 1 3.3 3.6 v write inhibit voltage v wi 2.5 2.7 3.0 1 v input high voltage v ih 2.2 v dd + 0.3 2 v input low voltage v il ?.5 3 0.8 v operating temperature MR0A16Ays35 (commercial) MR0A16Acys35 (industrial) MR0A16Avys35 (extended) t a 0 -40 -40 70 85 105 ?c notes: 1 after power up or if v dd falls below v wi , a waiting period of 2 ms must be observed, and e and w must remain high for 2 ms. memory is designed to prevent writing for all input pin conditions if v dd falls below minimum v wi . 2 v ih (max) = v dd + 0.3 vdc; v ih (max) = v dd + 2.0 vac (pulse width 10 ns) for i 20.0 ma. 3 v il (min) = ?.5 vdc; v il (min) = ?.0 vac (pulse width 10 ns) for i 20.0 ma.
electrical specifications MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 5 direct current (dc) table 5. dc characteristics parameter symbol min typ max unit input leakage current i lkg(i) 1 a output leakage current i lkg(o) 1 a output low voltage (i ol = +4 ma) (i ol = +100 a) v ol 0.4 v ss + 0.2 v output high voltage (i oh = ? ma) (i oh = ?00 ma) v oh 2.4 v dd ?0.2 v table 6. power supply characteristics parameter symbol typ max unit ac active supply current ?read modes 1 (i out = 0 ma, v dd = max) i ddr tbd tbd ma ac active supply current ?write modes 1 (v dd = max) i ddw tbd tbd ma ac standby current (v dd = max, e = v ih ) (no other restrictions on other inputs) i sb1 tbd tbd ma cmos standby current ( e v dd 0.2 v and v in v ss + 0.2 v or v dd 0.2 v) (v dd = max, f = 0 mhz) i sb2 tbd tbd ma notes: 1 all active current measurements are measured with one address transition per cycle. table 7. capacitance 1 parameter symbol typ max unit address input capacitance c in ?pf control input capacitance c in ?pf input/output capacitance c i/o ?pf notes: 1 f = 1.0 mhz, dv = 3.0 v, t a = 25?c, periodically sampled rather than 100% tested.
MR0A16A advanced information data sheet, rev. 0 6 freescale semiconductor electrical specifications figure 3. output load for ac test table 8. ac measurement conditions parameter value logic input timing measurement reference level 1.5 v logic output timing measurement reference level 1.5 v logic input pulse levels 0 or 3.0 v input rise/fall time 2 ns output load for low and high impedance parameters see figure 3a output load for all other timing parameters see figure 3b ab output r l = 50 v l = 1.5 v z d = 50 output 600 725 5 pf +3.3 v
timing specifications MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 7 timing specifications read mode table 9. read cycle timing 1, 2 parameter symbol min max unit read cycle time t avav 35 ns address access time t avqv ?5ns enable access time 3 t elqv ?5ns output enable access time t glqv ?5ns byte enable access time t blqv ?5ns output hold from address change t axqx 3ns enable low to output active 4, 5 t elqx 3ns output enable low to output active 4, 5 t glqx 0ns byte enable low to output active 4, 5 t blqx 0ns enable high to output hi-z 4, 5 t ehqz 015ns output enable high to output hi-z 4, 5 t ghqz 010ns byte high to output hi-z 4, 5 t bhqz 010ns notes: 1 w is high for read cycle. 2 due to product sensitivities to noise, power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read and write cycles. 3 addresses valid before or at the same time e goes low. 4 this parameter is sampled and not 100% tested. 5 transition is measured 200 mv from steady-state voltage.
MR0A16A advanced information data sheet, rev. 0 8 freescale semiconductor timing specifications figure 4. read cycle 1 1 figure 5. read cycle 2 t avav t axqx t avqv data valid previous data valid q (data out) a (address) notes: 1 device is continuously selected ( e v il , g v il ). t avav t avqv a (address) t elqx t glqv data valid e (chip enable) g (output enable) lb, ub (byte enable) q (data out) t elqv t glqx t blqv t blqx t bhqz t ghqz t ehqz
timing specifications MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 9 write mode table 10. write cycle timing 1 ( w controlled) 1, 2, 3, 4, 5 parameter symbol min max unit write cycle time 6 t avav 35 ns address set-up time t avwl 0ns address valid to end of write ( g high) t avwh 18 ns address valid to end of write ( g low) t avwh 20 ns write pulse width ( g high) t wlwh t wleh 15 ns write pulse width ( g low) t wlwh t wleh 15 ns data valid to end of write t dvwh 10 ns data hold time t whdx 0ns write low to data hi-z 7, 8, 9 t wlqz 012ns write high to output active 7, 8, 9 t whqx 3ns write recovery time t whax 12 ns notes: 1 a write occurs during the overlap of e low and w low. 2 due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 if g goes low at the same time or after w goes low, the output will remain in a high-impedance state. 4 after w, e, or ub/ lb has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 the minimum time between e being asserted low in one cycle to e being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 all write cycle timings are referenced from the last valid address to the first transition address. 7 this parameter is sampled and not 100% tested. 8 transition is measured 200 mv from steady-state voltage. 9 at any given voltage or temperature, t wlqz max < t whqx min.
MR0A16A advanced information data sheet, rev. 0 10 freescale semiconductor timing specifications figure 6. write cycle 1 ( w controlled) t avav t avwh a (address) t wleh data valid e (chip enable) w ( write enable) lb, ub (byte enable) q (data out) t dvwh t wlqz t whdx d (data in) t whax hi-z hi-z t avwl t wlwh t whqx
timing specifications MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 11 table 11. write cycle timing 2 ( e controlled) 1, 2, 3, 4, 5 parameter symbol min max unit write cycle time 6 t avav 35 ns address set-up time t avel 0ns address valid to end of write ( g high) t aveh 18 ns address valid to end of write ( g low) t aveh 20 ns enable to end of write ( g high) t eleh t elwh 15 ns enable to end of write ( g low) 7, 8 t eleh t elwh 15 ns data valid to end of write t dveh 10 ns data hold time t ehdx 0ns write recovery time t ehax 12 ns notes: 1 a write occurs during the overlap of e low and w low. 2 due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 if g goes low at the same time or after w goes low, the output will remain in a high-impedance state. 4 after w, e, or ub/ lb has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 the minimum time between e being asserted low in one cycle to e being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 all write cycle timings are referenced from the last valid address to the first transition address. 7 if e goes low at the same time or after w goes low, the output will remain in a high-impedance state. 8 if e goes high at the same time or before w goes high, the output will remain in a high-impedance state.
MR0A16A advanced information data sheet, rev. 0 12 freescale semiconductor timing specifications figure 7. write cycle 2 ( e controlled) t avav t aveh a (address) data valid e (chip enable) w (write enable) lb, ub (byte enable) q (data out) d (data in) t ehax hi-z t eleh t dveh t avel t elwh t ehdx
timing specifications MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 13 table 12. write cycle timing 3 ( lb/ ub controlled) 1, 2, 3, 4, 5, 6 parameter symbol min max unit write cycle time 7 t avav 35 ns address set-up time t avbl 0ns address valid to end of write ( g high) t avbh 18 ns address valid to end of write ( g low) t avbh 20 ns byte pulse width ( g high) t bleh t blwh 15 ns byte pulse width ( g low) t bleh t blwh 15 ns data valid to end of write t dvbh 10 ns data hold time t bhdx 0ns write recovery time t bhax 12 ns notes: 1 a write occurs during the overlap of e low and w low. 2 due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 if g goes low at the same time or after w goes low, the output will remain in a high-impedance state. 4 after w, e, or ub/ lb has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 if both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. 6 the minimum time between e being asserted low in one cycle to e being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 7 all write cycle timings are referenced from the last valid address to the first transition address.
MR0A16A advanced information data sheet, rev. 0 14 freescale semiconductor timing specifications figure 8. write cycle 3 ( lb/ ub controlled) t avav t bhax a (address) data valid e (chip enable) w (write enable) lb, ub (byte enable) q (data out) d (data in) hi-z hi-z t avbl t bleh t blwh t bhdx t dvbh t avbh
ordering information MR0A16A advanced information data sheet, rev. 0 freescale semiconductor 15 ordering information this product is available in commercial, industrial, and extended temperature versions. freescale's semiconductor products can be classified into the following tiers: "commercial", "industrial" and ?xtended. a product should only be used in applications appropriate to its tier as shown below. for questions, please contact a freescale sales representative. commercial ?typically 5 year applications - personal computers, pda's, portable telecom products, consumer electronics, etc. industrial, extended ?typically 10 year applications - installed telecom equipment, workstations, servers, etc. these products can also be used in commercial applications. part numbering system package information revision history table 13. package information device pin count package type designator case no. document no. rohs compliant MR0A16A 44 tsop type ii ys 924a-02 98ass23673w true revision history revision date description of change 0 18 jun 2007 initial advance information release (order by full part number) mr freescale mram memory prefix density code (0 = 1 mb, 1 = 2 mb, timing set (35 = 35 ns) revision (a = rev 1) i/o configuration (08 = 8 bits, 16 = 16 bits) 0 16 a a v ys 35 memory type (a = async, s = sync) 2 = 4 mb, 4 = 16 mb) package type (ys = tsop ii) operating temperature range (missing = 0 c to 70 c, c = -40 c to 85 c, v = -40 c to 105 c)
MR0A16A advanced information data sheet, rev. 0 16 freescale semiconductor mechanical drawing mechanical drawing the following pages detail the package available to MR0A16A.

MR0A16A rev. 0, 6/2007 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/paci?: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customers technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2004, 2006, 2007.

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